Many electronic devices employ buffers to interface with external signals. These buffers have certain respective delays associated therewith. In applications where an internal matching buffer is required to match the delay of an input buffer that brings an external signal inside of a semiconductor chip, achieving good matching over process, supply voltage, and temperature (PVT) variations to which the chip may be subjected is often difficult. One exemplary application in which it is desirable to use an internal matching buffer is for phase alignment in a phase-locked loop (PLL) circuit, where the chip level design requires the removal of clock tree build-up delay and/or removal of the delay of the reference clock input buffer delay.
In many earlier technologies, core logic circuitry typically operated at the same supply voltage as input/output (IO) circuitry and used the same type of transistors. In this instance, the circuitry of the input buffer was mimicked by the matching buffer so as to provide good delay matching. Using modern technology, however, the core logic circuitry often operates at a lower supply voltage than the IO circuitry. Moreover, core logic circuitry, as may be used in the matching buffer, typically employs transistors having a low threshold voltage associated therewith, often referred to as low-voltage transistors, while IO circuitry, as may be used in the input buffer, employs transistors having a high threshold voltage associated therewith, often referred to as high-voltage transistors. Because of the different supply voltages at which the two types of transistors operate and the different process parameters associated with the two types of transistors, correlation between the IO circuitry and the core logic circuitry is typically difficult to achieve without performing a costly trimming procedure and/or adding internal delay matching circuitry (e.g., matching buffer).
In multiple voltage supply applications, one known matching methodology might involve using the same circuitry for both the input buffer and the matching buffer, to thereby provide correlation between the input buffer and the matching buffer, and to utilize voltage level translation circuitry for translating between the core voltage used by the core logic circuitry and the IO voltage used by the IO circuitry. This technique, however, suffers from the added delay introduced by the voltage level translation itself, which will cause some degree of mismatch. Another technique is to design the overall system to match an average delay and then to accommodate for the differences in the two delays by increasing the chip timing budget. This technique, however, can undesirably increase chip gate count per unit area and can decrease the maximum speed at which the chip can function reliably.
Accordingly, there exists a need for an improved buffer circuit architecture for providing enhanced delay matching, which does not suffer from one or more of the problems exhibited by conventional buffer circuit architectures.